by Dilnoza Bobokalonova

RISC vs CISC

RISC (Reduced Instruction Set Computing) technology is prevalent in many modern 32-bit microcontrollers. Unlike CISC (Complex Instruction Set Computing) processors, RISC engines typically execute each instruction in a single clock cycle, leading to faster execution compared to CISC processors operating at the same clock speed.

However, this enhanced performance comes with a trade-off: RISC processors generally require more memory to store the same program compared to CISC processors. Complex functions that can be executed in a single, albeit slower, instruction in a CISC processor may necessitate two, three, or more simpler instructions in a RISC architecture.

In most embedded devices, except those requiring utmost speed, the cost of memory outweighs the importance of processor execution speed. To mitigate memory requirements and reduce costs, Advanced RISC Machines (ARM) developed the Thumb instruction set as an option for their RISC processor cores. One of the most well-known chips incorporating the Thumb instruction set is the ARM7TDMI, with the "T" in the core's name indicating Thumb support.

ARM vs Thumb

The Thumb instruction set is a compact form of shorthand for a subset of the 32-bit instructions found in standard ARM architecture. While each Thumb instruction can be executed equivalently using a 32-bit ARM instruction, not all ARM instructions are available in the Thumb subset. For instance, access to status or coprocessor registers is not possible within Thumb instructions. Additionally, some tasks that can be accomplished with a single ARM instruction may require a sequence of Thumb instructions.

In contrast, ARM architecture only employs a 32-bit instruction set. When operating in the Thumb state, the processor expands the shorter 16-bit instructions fetched from memory into their corresponding 32-bit equivalents. However, the difference between equivalent instructions lies in their fetching and interpretation before execution, rather than in their functionality. The hardware within the chip handles the expansion from 16-bit to 32-bit instructions, ensuring execution efficiency without any slowdown. Moreover, the use of narrower 16-bit instructions offers memory advantages.

The Thumb instruction set caters to most functionalities typically needed in applications, including arithmetic and logical operations, load/store data movements, and conditional and unconditional branches. Consequently, code written in C can be successfully executed in Thumb state based on the available instruction set. However, it's common for device drivers and exception handlers to be written at least partially in ARM state to handle specific functionalities or exceptions effectively.

• R0 to R15: These are general-purpose registers in the ARM architecture. Registers R0 to R12 are used for general purposes by convention, but they can technically be used for anything.
• R13 (SP): The Stack Pointer (SP), it points to the last item in the stack.
• R14 (LR): The Link Register (LR), it stores the return address when a subroutine is called.
• R15 (PC): The Program Counter (PC), it holds the address of the next instruction to be executed.
• CPSR: The Current Program Status Register, which holds flags that are changed as a result of arithmetic and logical operations (such as Zero, Negative, Carry, Overflow) and control bits which define the operating state of the processor.

But clearly, we have the difference with the Thumb model, due it being the 16-bit, compressed version of the ARM state. To quote an article:

The biggest register difference involves the SP register. The Thumb state has unique stack mnemonics (PUSH, POP ) that don’t exist in the ARM state. These instructions assume the existence of a stack pointer, for which R13 is used. They translate into load and store instructions in the ARM state.

The CPSR register holds the processor mode (user or exception flag), interrupt mask bits, condition codes, and Thumb status bit. The Thumb status bit (T ) indicates the processor’s current state: 0 for ARM state (default) or 1 for Thumb. Although other bits in the CPSR may be modified in software, it’s dangerous to write to T directly; the results of an improper state change are unpredictable.

<aside> 💡 In the Thumb instruction set, instructions are 16 bits long, which results in more compact code compared to the standard 32-bit ARM instructions. This compactness reduces the amount of memory required to store the program, which can be beneficial in embedded systems where memory is often limited and costly.

However, because not all instructions can be represented in the Thumb instruction set, some parts of the code may need to use standard 32-bit ARM instructions. In these cases, where Thumb instructions are not suitable or efficient, the processor needs to switch to ARM mode to execute those instructions. This switch incurs a penalty in terms of performance because it takes additional clock cycles to fetch and execute the 32-bit instructions. + It is same penalty if we remain in Thumb mode and fetch ARM instruction sets in 2 bus cycles per instruction.

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